Layout structure for CMOS circuit

ABSTRACT

A layout structure for a CMOS circuit comprises a transistor layer forming P-type transistors  11  and  21  and N-type transistors  12  and  22,  and a resistor layer which includes a resistor  13  formed to have a predetermined length and to make plural appropriate portions or the entire of the resistor along a direction of the length satisfy a mask rule necessary for providing VIAs, the resistor being connected to appropriate connecting portions of the P-type transistors and the N-type transistors through the VIAs by metal wires  31  formed of a metal layer, and the resistor having a predetermined circuit resistance which can be set based on the positions of the appropriate connecting portions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a layout structure for a CMOS circuit,and particularly to a layout structure for a CMOS circuit which allowseasy delay adjustment.

2. Description of the Related Art

In conventional CMOS circuits, timing adjustment is conducted at variouspoints. For example, a delay circuit having an adjusted delay value isused for pulse width adjustment in chopping a clock signal to pulsate.FIG. 5 is a timing chart showing operations of the pulse widthadjustment. A pulse signal (CK) denoted at (a) in FIG. 5 is delayed andinverted as indicated by (b). From the result of this and the originalcircuit, NAND is obtained so that a pulse as denoted at (c) can beobtained with a pulse width equal to a delay value. In this case, if thepulse width is too large, racing occurs on a path from the master outputof a latch. Otherwise, if the pulse width is too small, no value may belatched or a delay value to a slave output may have an error.

Other examples are delay adjustment for restricting racing within arange in which no over-delay occur and clock phase adjustment foradapting flexibly an inter-cycle period to fit a data transfer velocity.

Although these adjustments are adopted in design stages, it oftenappears that designed adjustment values cannot be achieved in frequentcases due to problems of immature manufacturing processes or variouscalculation errors. In those cases, actual chips are fed back andsubjected to measurements to specify the reasons. Thus, manufacturingdata, e.g., the layout structure of the chips is modified, and the chipsare remanufactured so that the designed adjustment values can beachieved.

With respect to layout structures of CMOS circuits, various techniquesare known conventionally (for example, see Patent Literature 1: JapanesePatent Laid-Open No. 62-277747).

In such a modification of a layout structure in the prior art, widthsand lengths of transistors are adjusted in general cases. For thispurpose, the layout structure has to be modified totally throughout adiffusion layer (transistor layer), a resistor layer, and a metal layer(metal wire layer), and so requires a very long time and huge costs.

Meanwhile, if the modification of the layout structure can be achievedwith a modification only to the metal layer as an upper layer, thelayout structure adopted in chips being manufactured can be partiallyreflected directly on the lower layers such as resistor and diffusionlayers below the metal layer. Then, not only the turn-around time can bereduced but also the costs required for manufacturing masks can besaved.

The present invention has been made to solve these conventional problemsand has an object of providing a layout structure for a CMOS circuit inwhich a modification for delay adjustment to the layout structure of theCMOS circuit can be achieved by modifying only a metal layer as an upperlayer, so that turn-around time can be reduced and mask manufacturingcosts can be saved.

SUMMARY OF THE INVENTION

To achieve the above object, in the present invention, outputs of P-typeand N-type transistors are connected by wires of a high-resistancelayer, at gates in the driver side, to make a potential difference ableto occur between the outputs of the P-type and N-type transistors.Further, the wires made of a high-resistance layer are made able to bebypassed by a metal layer, so that the resistance value can be varied bymodifying the metal layer. In this respect, VIAs need to be providedbetween the metal layer and the high-resistance layer. The layout ishence arranged to satisfy mask rules even after VIAs are provided.Meanwhile, the circuit at gates in the receiver side is configured suchthat inputs of N-type and P-type transistors are separated from eachother and are connected through a resistor of the gates in the driverside by the metal layer.

In another layout structure having the same circuit configuration asdescribed above, the outputs of the P-type and N-type transistors areseparated from each other at the gates in the driver side. At the gatesin the receiver side, the inputs of the P-type and N-type transistorsare connected by wires of a high-resistance layer, so that the pointconnecting the output of the driver or the resistance value can bevaried by a modification to the metal layer.

More specifically, according to an aspect of the present invention, alayout structure for a CMOS circuit having a P-type transistor and anN-type transistor comprises: a transistor layer forming the P-typetransistor and the N-type transistor; and a resistor layer whichincludes a resistor formed to have a predetermined length and to makeplural appropriate portions or all of the resistor along a direction ofthe length satisfy a mask rule necessary for providing VIAs, theappropriate portions of the resistor being connected to appropriateconnecting portions of the P-type transistor and the N-type transistorthrough the VIAs by metal wires formed of a metal layer, and theresistor having a predetermined circuit resistance which can be setbased on the appropriate connecting portions.

In the layout structure for the CMOS circuit, the resistor formed in theresistor layer can be partially bypassed through the VIAs by the metalwires formed of the metal layer.

Also in the layout structure for the CMOS circuit, the P-type transistorand the N-type transistor formed in the transistor layer may be pairedwith each other, forming a driver circuit in a front stage and areceiver circuit in a next stage, and the resistor formed in theresistor layer may connect the driver circuit and the receiver circuitto each other through part of the resistor by the metal wires formed inthe metal layer.

Further, in the layout structure for the CMOS circuit, the drivercircuit and the receiver circuit may be connected to each other in aconnection structure which is either a parallel type or a cross type.The resistor formed in the resistor layer may be connected to gates ofthe transistors forming the receiver circuit.

According to another aspect of the present invention, a layout structurefor a CMOS circuit having a P-type transistor and an N-type transistorcomprises: a transistor layer forming the P-type transistor and theN-type transistor; and a resistor layer which includes a resistorinserted between an output end of the P-type transistor and an outputend of the N-type transistor and formed to make plural appropriateportions or all of the resistor satisfy a mask rule necessary forproviding VIAs, the resistor being able to be bypassed through the VIAsby metal wires formed of a metal layer, to set a resistance valuebetween the output ends of the P-type transistor and the N-typetransistor.

In the layout structure for the CMOS circuit, a high-resistance wirebased on polysilicon or local interconnection may be used as theresistor formed in the resistor layer.

According to further another aspect of the present invention, a layoutstructure for a CMOS circuit having a P-type transistor and an N-typetransistor comprises: a transistor layer forming the P-type transistorand the N-type transistor; a resistor layer which includes a resistorformed to have a predetermined length and to make plural appropriateportions or all of the resistor along a direction of the length satisfya mask rule necessary for providing VIAs; and a metal layer whichincludes metal wires capable of connecting the appropriate portions ofthe resistor to appropriate connecting portions of the P-type transistorand the N-type transistor through the VIAs, and capable of setting apredetermined circuit resistance based on the appropriate connectingportions, by the resistor.

According to further another aspect of the present invention, a layoutstructure for a CMOS circuit having a P-type transistor and an N-typetransistor comprises: a transistor layer forming the P-type transistorand the N-type transistor; a resistor layer which includes a resistorinserted between an output end of the P-type transistor and an outputend of the N-type transistor, and formed to make plural appropriateportions or all of the resistor satisfy a mask rule necessary forproviding VIAs; and a metal layer which includes metal wires capable ofbypassing a part or all of the resistor through the VIAs, to set aresistance value between the output ends of the P-type transistor andthe N-type transistor.

As specifically described above, according to the present invention, theresistance value can be varied by modifying only the metal layer or thepotentials of the P-type and N-type transistors can be adjusted byswitching cross/parallel of connections between the driver and thereceiver. The delay can thus be adjusted. If this layout structure isadopted, circuits can have a general transistor size avoiding a tooshort transistor width or too long transistor length. As a result,matching with a circuit simulation model can be improved and variantscan be prevented from increasing. Thus, according to the presentinvention, actual chips can reflect a delay adjustment in a short time.The layer to be modified in the delay adjustment is restricted. Costscan hence be reduced. Further advantages are attained in that errors insimulation models and use of transistors having great variants can beavoided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C show layout structures of a CMOS circuit in theembodiment 1, wherein FIG. 1A shows a layout before setting a resistancevalue (before modification), FIG. 1B shows the circuit shown in FIG. 1Awith use of circuit symbol marks, and FIG. 1C shows a layout aftersetting a resistance value (after modification);

FIGS. 2A to 2C show resistors in a resistor layer wherein FIG. 2A showsa conventional resistor, FIG. 2B shows a resistor having plural VIAconnecting positions, and FIG. 2C shows a resistor which can entirelyserve as VIA connecting positions;

FIGS. 3A to 3C show layout structures of a CMOS circuit according to theembodiment 2 wherein FIG. 3A shows a layout before setting a resistancevalue (before modification), FIG. 3B shows the circuit shown in FIG. 3Awith use of circuit symbol marks, and FIG. 3C shows a layout aftersetting a resistance value (after modification);

FIGS. 4A to 4D show layout structures of a CMOS circuit according to theembodiment 3 wherein FIG. 4A shows a layout before setting a resistancevalue (before modification), FIG. 4B shows the circuit shown in FIG. 4A,using circuit symbol marks, FIG. 4C shows a layout after setting aresistance value (after modification), and FIG. 4D shows the circuitshown in FIG. 4C with use of circuit symbol marks; and

FIG. 5 is a timing chart showing operations of pulse width adjustment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will now be described withreference to the drawings.

[Embodiment 1]

FIGS. 1A to 1C show layout structures of a CMOS circuit in anembodiment 1. FIG. 1A shows a layout before setting a resistance value(before modification). FIG. 1B shows the circuit shown in FIG. 1A, usingcircuit symbol marks. FIG. 1C shows a layout after setting a resistancevalue (after modification).

The CMOS circuit shown in FIG. 1 is constructed by a driver 10 in afront stage and a receiver 20 in a rear stage. The driver 10 in thefront stage has a P-type transistor 11, an N-type transistor 12, and aresistor 13 inserted between outputs of the transistors 11 and 12. Thereceiver 20 in the rear stage is constructed by a P-type transistor 21and an N-type transistor 22. In these transistors 21 and 22, source S,gates G, and drains D are formed in the diffusion layer (transistorlayer), and electrodes S′, G′, and D′ thereof are formed below the metallayer which will be described later. For example, the gate electrodes G′may be formed with use of polysilicon, and the source electrodes S′ anddrain electrodes D′ are formed with use of silicon. Metal wires are ledand connected to these electrodes, as shown in the figures.

The resistor 13 is formed to obtain a circuit resistance (apredetermined circuit resistance) between the transistors 11 and 12. Forexample, high-resistance wires based on polysilicon or localinterconnection are used and formed in the resistor layer. The metallayer formed above the resistor layer has a very low resistance valueand therefore, needs an impracticable length to create such a resistancevalue that influences circuit operations. If the resistance value isthus forcedly created, a very large area is consumed and a large part ofwiring areas is consumed. This makes it difficult to connect logic gatesto each other. Although the resistor can be formed of a diffusion layer,the resistor can be created with a relatively smaller area and arelatively short distance by forming the resistor of a high-resistancewire made of polysilicon or the like.

The resistor 13 is formed to have a predetermined length between thedrain electrodes (or nodes close to the drain electrodes) of the P-typetransistor 11 and the N-type transistor 12 of the driver 10. Thisresistor 13 is previously formed to be long so that the resistance valueis greater relative to the design value. In the present embodiment, theshape of the resistor is formed in a substantially rectangular U-shapein which an open part 13 a is faced to the drains of the driver 10 and aclose part 13 b is faced to the drains of the receiver 20. As shown inFIG. 2B, plural portions 13 c in the length direction thereof are formedto satisfy mask rules necessary for a VIA layout. Alternatively, asshown in FIG. 2C, the entire resistor 13 in its length direction may beformed to satisfy the mask rules necessary for the VIA layout. Note thatFIG. 2A shows a conventional wire resistor and no VIA can be formed atany portion of the conventional resistor.

Next, metal wires 31 are formed in the metal layer. This metal layer isprovided above the diffusion layer (transistor layer) and resistor layerdescribed above. Further, as shown in FIG. 1B, the metal wires 31connect, in parallel, the drain electrodes of the P-type transistor 11and N-type transistor 12 of the driver 10 and the gate electrodes of theP-type transistor 21 and N-type transistor 22 of the receiver 20,respectively. A predetermined portion 13B which includes the close part13 b of the resistor 13 formed in substantially rectangular U-shape, isbypassed if necessary.

When the resistance value is modified (decreased) based on an evaluationresult with respect to an actual device, the bypass position 13A (13C)is set according to the modification amount. That is, the move thebypassing amount is increased, the move the resistance value can be madesmall. In this case, the resistor 13 is previously formed such that theresistance value is relatively great, and plural portions or all of theresistor is formed to allow provision of VIAs. Therefore, the resistancevalue can be varied easily (i.e., a design modification can be carriedout to satisfy an evaluation value) by only modifying (selecting andconnecting appropriate VIAs) connecting positions (bypass positions) ofthe metal wires in the metal layer.

As described above, in the embodiment 1, the resistor 13 is insertedbetween the P-type transistor 11 and N-type transistor 12 of the driver10, and the P-type transistor 21 and N-type transistor 22 of thereceiver 20 are connected to each other through a metal layer. TheP-type transistor 11 of the driver 10 is connected to the P-typetransistor 21 of the receiver 20, as well as the N-type transistor 12 ofthe driver 10 to the N-type transistor 22 of the receiver 20, inparallel.

At this time, the drain (or node close to the drain) of the P-typetransistor 11 of the driver 10 easily becomes close to the VDDpotential. Therefore, the drive ability of the P-type transistor 21 ofthe receiver 20 is weakened. Likewise, the drive ability of the N-typetransistor 22 of the receiver 20 is weakened. If part or all of theresistor 13 is bypassed through the metal wires 31, the resistance valuecan be reduced so that the above-mentioned effect of weakening the driveability can be reduced. A layout modification of this kind to adjust thedrive ability can be achieved by modifying only the metal layer in thelayout structure. In the present embodiment, the resistor 13 is formedin a rectangular U-shape having a close portion 13 c. It is hencepossible to obtain a large bypass amount from such an amount of shortmetal wires that bypasses the close portion 13 c. A greater reduction inthe resistance value can be easily obtained.

[Embodiment 2]

FIGS. 3A to 3C show layout structures of a CMOS circuit according to theembodiment 2. FIG. 3A shows a layout before setting a resistance value(before modification). FIG. 3B shows the circuit shown in FIG. 3A, usingcircuit symbol marks. FIG. 3C shows a layout after setting a resistancevalue (after modification). Reference symbols identical to those inFIGS. 1 denote the identical components.

The foregoing embodiment 1 has been described in the case where themetal wires between the driver 10 and the receiver 20 are parallel toeach other. The present embodiment 2 will be described in the case wherethe metal wires cross each other.

Also in the present case, the resistor 13 is inserted between the P-typetransistor 11 and N-type transistor 12 of the driver 10. However, theP-type transistor 21 and N-type transistor 22 of the receiver 20 arecross-connected, i.e., the P-type transistor 11 of the driver 10 isconnected to the N-type transistor 22 of the receiver 20, as well as theN-type transistor 12 of the driver 10 to the P-type transistor 21 of thereceiver 20, through metal wires (a metal layer) as shown in FIG. 3A.

At this time, the drain (node) of the P-type transistor 11 of the driver10 becomes easily close to the VDD potential. Therefore, the driveability of the N-type transistor 22 of the receiver 20 is strengthened.Likewise, the drive ability of the P-type transistor 21 of the receiver20 is strengthened. The resistance value can be reduced by bypassingpart or all of the resistor through the metal layer, so that theabove-mentioned effect of strengthening the drive ability can bereduced. A layout modification of this kind to adjust the drive abilitycan be achieved by modifying only the metal layer in the layoutstructure.

[Embodiment 3]

FIGS. 4A to 4D show layout structures of a CMOS circuit according to theembodiment 3. FIG. 4A shows a layout before setting a resistance value(before modification). FIG. 4B shows the circuit shown in FIG. 4A, usingcircuit symbol marks. FIG. 4C shows a layout after setting a resistancevalue (after modification). FIG. 4D shows the circuit shown in FIG. 4C,using circuit symbol marks. Reference symbols identical to those inFIGS. 1 denote the identical components.

In the embodiment 3, the resistor 13 is provided to connect the gateelectrodes G′ of the P-type transistor 21 and N-type transistor 22 ofthe receiver 20, through VIAs near these transistors. The drains (nodes)of the P-type transistor 11 of the driver 10 and the N-type transistor12 of the driver 10 are connected to appropriate two portions 13 c″ ofthe gate electrodes G′. In this connection relationship, as shown inFIG. 4B, the driver 10 and the receiver 20 are parallel to each other(like FIG. 3A). The resistor 13 has a substantially rectangular U-shapelike in the case of FIGS. 1. However, the open portion 13 a of theresistor 13 is faced in an opposite direction to that in the case ofFIGS. 1. Specifically, the open portion 13 a is open toward the receiver20. The two open ends of this portion are respectively connected to thegate electrodes (or nodes close to the gate electrodes) of thetransistors 21 and 22 of the receiver 20.

In contrast, as shown in FIG. 4C, the connecting positions of metalwires on the resistor 13 are modified (from 13 c″ to 13 c′″). Then, theresistance value between the P-type transistor 11 and N-type transistor12 of the driver can be changed, and the connection between the driver10 and the receiver 20 can be modified to a cross type as shown in FIG.4D.

That is, the outputs of the P-type transistor 11 and N-type transistor12 of the driver 10 are connected through a metal layer to connectingpoints among the input nodes of the receiver 20. By selecting theconnecting points, a choice of parallel or cross is available, and theresistance value (or predetermined circuit resistance) between theP-type transistor 11 and the N-type transistor 12 can be varied. Inaddition, the resistance value (or predetermined circuit resistance)between the P-type transistor 21 and the N-type transistor 22 can bevaried by bypassing part of the resistor.

1. A layout structure for a CMOS circuit having a P-type transistor andan N-type transistor, comprising: a transistor layer forming the P-typetransistor and the N-type transistor; and a resistor layer whichincludes a resistor formed to have a predetermined length and to makeplural appropriate portions or all of the resistor along a direction ofthe length satisfy a mask rule necessary for providing VIAs, theappropriate portions of the resistor being connected to appropriateconnecting portions of the P-type transistor and the N-type transistorthrough the VIAs by metal wires formed of a metal layer, and theresistor having a predetermined circuit resistance which can be setbased on the appropriate connecting portions.
 2. The layout structurefor the CMOS circuit, according to claim 1, wherein the resistor formedin the resistor layer can be partially bypassed through the VIAs by themetal wires formed of the metal layer.
 3. The layout structure for theCMOS circuit, according to claim 1, wherein the P-type transistor andthe N-type transistor formed in the transistor layer are paired witheach other, forming a driver circuit in a front stage and a receivercircuit in a next stage, and the resistor formed in the resistor layerconnects the driver circuit and the receiver circuit to each otherthrough part of the resistor by the metal wires formed in the metallayer.
 4. The layout structure for the CMOS circuit, according to claim3, wherein the driver circuit and the receiver circuit are connected toeach other in a connection structure which is either a parallel type ora cross type.
 5. The layout structure for the CMOS circuit, according toclaim 3, wherein the resistor formed in the resistor layer is connectedto gates of the transistors forming the receiver circuit.
 6. A layoutstructure for a CMOS circuit having a P-type transistor and an N-typetransistor, comprising: a transistor layer forming the P-type transistorand the N-type transistor; and a resistor layer which includes aresistor inserted between an output end of the P-type transistor and anoutput end of the N-type transistor and formed to make pluralappropriate portions or all of the resistor satisfy a mask rulenecessary for providing VIAs, the resistor being able to be bypassedthrough the VIAs by metal wires formed of a metal layer, to set aresistance value between the output ends of the P-type transistor andthe N-type transistor.
 7. The layout structure for the CMOS circuit,according to claim 1, wherein a high-resistance wire based onpolysilicon or local interconnection is used as the resistor formed inthe resistor layer.
 8. A layout structure for a CMOS circuit having aP-type transistor and an N-type transistor, comprising: a transistorlayer forming the P-type transistor and the N-type transistor; aresistor layer which includes a resistor formed to have a predeterminedlength and to make plural appropriate portions or all of the resistoralong a direction of the length satisfy a mask rule necessary forproviding VIAs; and a metal layer which includes metal wires capable ofconnecting the appropriate portions of the resistor to appropriateconnecting portions of the P-type transistor and the N-type transistorthrough the VIAs, and capable of setting a predetermined circuitresistance based on the appropriate connecting portions, by theresistor.
 9. A layout structure for a CMOS circuit having a P-typetransistor and an N-type transistor, comprising: a transistor layerforming the P-type transistor and the N-type transistor; a resistorlayer which includes a resistor inserted between an output end of theP-type transistor and an output end of the N-type transistor, and formedto make plural appropriate portions or all of the resistor satisfy amask rule necessary for providing VIAs; and a metal layer which includesmetal wires capable of bypassing a part or all of the resistor throughthe VIAs, to set a resistance value between the output ends of theP-type transistor and the N-type transistor.